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Towards Fixing SMS Cards

Goal of this page - Be of service to people maintaining SMS cards.

A quick history:

  1. Our first SMS card fixer (2004-2009) was Tim Coslet (now in Montana).
    One of his favorite aids was this in-circuit transistor tester. Using a transistor curve-tracer, some odd characteristics were observed.
    Part of his tool kit were REALLY sharp probes to penetrate any protective coating or corrosion.
  2. Also during (2004-2009) there were considerable dialogs (Tim did not comment) about making further aids and test fixtures. Grant Saviers made this specification and this proposed front panel. Grant has also sent SMS card-tester-schematics-v20-Controls-1.pdf, SMS-card-tester-schematics-V20-Logic-1.pdf, CTDL-PNP-cards-tested_files, CTDL-NPN-cards-tested_files, STDTL-cards-tested_files
  3. Then Jim Hunt, unofficial postmaster of Burning Man, fixed our SMS cards. His favorite diagnostic tool was an ohm meter. He would fix a card, get it checked in the 1401 by Ron Williams, and if fixed, returned to service or spares. (or something like that ) Unfortunately for us, Jim got a real job :-((
  4. Over the years considerable inventory and card usage, Unit Plugging Charts, Plugging Sorted By SMS, Usage & Spares and other SMS card data collection/processing was performed -
  5. Starting in 2013 attention focused on specifying the new 1401 demonstration room and move in items to accomodate the changes.
  6. Nov 2013, 1401 room is renovated, equipment re-installed, mostly working as usual,
    and we have about 10 defective cards to fix, and no clear plan.


Table of Contents
     - Grant Savier's SMS card tester specification.
     - proposed front panel
     - SMS card tester schematics v20 Controls 1.pdf
     - SMS card tester schematics V20 Logic 1.pdf
     - CTDL PNP cards tested_files
     - CTDL NPN cards tested_files
     - STDTL cards tested_files


Grant Savier's SMS card tester specification.

IBM 1401 SMS card tester design trade-offs & Specifications

V6 Grant Saviers, 12/24/2008

Goals:

 

The goals are to increase the quality (coverage) of module tests, facilitate fixing the broken module backlog, introduce some stress/margin testing at the card level, and to make it possible to consider wholesale or partial wholesale testing of modules.

 

An approach to improving system uptime using this tester is:

 

1.     Thoroughly test a useful population of the spares as “reference cards”. These cards should be marked in a manner acceptable to the Museum.

2.     Cycle through critical areas of the machine, upgrading to reference cards and upgrade removed cards to reference quality as we go, and verifying correct operation in each cycle

 

Tester Design: Several dimensions of trade-offs have been considered over the last two years:

 

Complexity-flexibility-capability tradeoffs: I rejected early on any programmable device as too complex, too difficult to understand, and too difficult to maintain. I think with some modest effort we could get an obsolete analog IC tester given to us and convert it to SMS cards, but consider the resources that would consume! Experience on the TAU Analyzer has demonstrated that real-time programming is hard to get done. Plus, the challenge of learning and tracking PC software standards & drivers and RT software design environments is substantial and not doable on a part time basis. The design, build, and test, and fixing of the tester shouldn’t soak up too many cycles from restoring the machine.

 

Test automation vs scope probing: We have to fix these modules at the component level, so there is not much benefit to providing any go/no go level of test results for known defective cards. Furthermore, the observed failures often include partial degradation in the performance of the semiconductors. A scope provides a quick visual check of gain, speed, and what is normal. These are much harder to do with a computer.

 

SMS test signal generation: There are a number of possibilities I’ve considered from simple limited functionality, to more complex, and very flexible. I thought in the end that the tester ought to test all gate level modules, or that a tester specific to each logic’s electrical characteristics be constructed. This tester provides preset levels for each logic card family used in the 1401 and adjustable levels for situations where they may be useful. It should be able to test all cards that are gates – AND, OR, NAND, NOR, XOR, etc.

Setting up a test: Should there be a quickly re-useable test setup and if so how? What kind of card “personality” memory? The problem needs a crossbar switch to be able to connect any test, load resistor, or power supply signal to any pin. The proposed solution is to use a pair of wire wrap tail 96 pin connectors, a female pin receptacle wired to all internal tester signals and a removable male pin plug that can be wired as appropriate to test a specific module. Again, this is simple technology, easy to understand and build, and reliable. Several card types have the same input and output pins and within each type there are frequently versions with no, 1, 2, 3, or 4 loads. A single plug could cover a number of these types if the load resisters and switches for them are mounted on the plug connector (via a small PCB). However, this capability is not included in the first generation tester in order to simplify the construction and to try the tester design prior to committing to the implementation.

 

Margin testing: 1. Power supply margining: Initially considered but then rejected in favor of variable input amplitudes and test frequency and perhaps (tbd) test signal risetimes. 2. Temperature testing: Peltier devices can be used to heat one side of a chamber and simultaneously cool the other. This could be added a later time and is not provided in the initial version.

 

Tester Maintenance: Given the number of cards to test, it should be easy to replace connectors, switches or other items that wear out.

 

 


Preliminary User Manual – SMS Card Tester

 

  1. Obtain the card schematic and test procedure.
  2. Wire the jumper block per the test procedure sheet
  3. Recheck the wiring.
  4. Power up the tester.
  5. Set the HI PULSE and LO PULSE levels, CLOCK FREQ, and COUNTER/PULSE switches per the test procedure.
  6. Set up the oscilloscope controls per the test procedure & connect the probes as specified.
  7. Plug in the card to be tested.
  8. Power up the card
  9. Switch the PROBE switch to the specified card pins, observe the waveforms and check them against the test procedure requirements.
  10. If any outputs are in error, probe the card for defective components.
  11. Replace all defective components and retest the card.

SMS Card Test Fixture Generation II

Draft Specification V6

Grant Saviers

12/24/08

 

1.0            Goals

1.1            Facilitate speedy and accurate test and diagnosis of single width SMS cards, with some margin test capabilities.

1.1.1       Provide a tester that can test the most numerous cards – e.g. gates with 4 or less inputs. Cards with internal states may or may not be possible to test with this tester. Exception: the CW trigger can be tested.

1.1.2       SMS cards with multiple identical logic functions will be tested with the inputs connected in parallel. While certain failures may yield cross coupling errors these are believed to be infrequent and easily identified by probing the card under test.

1.1.3       The etch side of the card will be visible to the operator.

1.2            (Not provided in Tester V1) Optionally preserve custom test setups for each card for quick setups via a “personality” connector configured uniquely for each card type.

1.3            Provide push pin solderless breadboard space for configuring tests, supply voltages, test signals, and loads.

1.4            Provide self contained fixed voltage power supplies.

1.5            Provide self contained test signals sufficient to test most logic cards

1.5.1       Signal levels are adjustable to permit margin testing.

1.5.2       Signal frequency is adjustable to permit margin testing.

1.5.3       Signal rise/fall times may be selectable (tbd)

 

2.0            Scope of modules tested

2.1            Single width standard 16 pin with +/-12 and +/-6 power voltages SMS cards.

2.2            Power supply pins are not predetermined.

2.3            No provision is made within the tester for other power supply voltages. However, in some cases an external supply and load could be used if the logic input levels of the card being tested are within the capability of the tester.

2.4            Approximately 91 card types of those identified as 1041 CPU cards in Ed Thelen’s spreadsheet should have all diodes and transistors tested by this tester. Fan in tie points are not tested and resistor inputs auxiliary to 4 input gates are not tested. These 91 cards comprise 2148 of the cards in the machine. (analysis spreadsheet available).

2.5            Peripheral card types and quantities need to be evaluated.

2.6            Schematics are not available for a number of cards, particularly in the TAU, so these need to be evaluated as well.

 

3.0            Test environment & setup

3.1            An oscilloscope is required to measure card inputs and outputs and the user must understand the function, internal state, board layout, and schematic of each card being tested.

 

4.0            Test signals

4.1            Four separate logic test signals are produced, with voltages compatible with the SMS logic requirements.

4.2            The test signal levels provided by the tester should be established prior to plugging in the card under test to prevent accidental damage by excessive drive voltages.

4.3            Test signals area generated by 74HC logic, driven by a self contained VFO with a user adjustable frequency range of 300 KHz to 3 MHz.

4.3.1       A separate input and selector switch is provided for clock frequencies outside this range. Signals should be 0 to 5v nominal into sensed by a 74HC14 Schmidt trigger gate protected by a series 100 ohm resistor and clamping diode.

4.4            The VFO clocks a 4 bit synchronous binary counter. Two modes of test signals are provided from the counter and are switch selectable:

4.4.1       Each bit of the counter is converted to a separate test signal compatible with SMS series logic, thus providing all possible input combinations for up to 4 input gates.

4.4.2       Each counter state is decoded to single pulses of one clock period duration. Counter states 2,6,10,14 are separately produced on the four test signal outputs. (note: this feature is designed particularly for the CW trigger card as the machine contains 124 of this type. It may be useful for other cards with internal state if the 4 pulses of same high and low levels can be used.) Controlled by two position toggle switch marked TEST SIGNALS: COUNTER - PULSE

4.4.3       For convenience in setting the test signal levels a 3 position toggle switch is provided to set all test signals to their high or low voltage. This switch is marked TEST SIGNALS: ALL HI – OSC -ALL LO. This switch overrides the COUNTER-PULSE switch when set to ALL HI or ALL LO

 

4.5            The SMS logic test signals are independently adjustable for HIGH LEVEL and LOW LEVEL test signal pulse levels, although all 4 signals have the same high and low values.

4.5.1       Five internal potentiometer sets (1 for high, 1 for low) are provided as preset levels and selected by a front panel rotary switch. A sixth switch position selects two front panel pots for arbitrary setting of test levels.

4.5.2       HIGH LEVEL may be set between +13v and -13.0v via a panel mounted potentiometer.

4.5.3       LOW LEVEL may be set between +13.0v and -13.0v via a panel mounted potentiometer.

4.5.4       Approximate levels will be marked for the front panel pots.

4.5.5       Two digital voltmeters (DVM’s) continuously monitor the HIGH LEVEL and LOW LEVEL. These DVMs are powered by a separate 12 vdc supply as the supply must be floating relative to the signals being measured.

4.5.6       HIGH must be greater than the LOW set points at all times. If they are not, a relay protection circuit sets all test signal outputs to 0.0v and lights an LED and (possible) audible audible alarm.

4.5.7       The front panel levels may be set while a module is under test; however there is no protection for exceeding the permissible SMS card under test input levels other that the current limiting of the Analog Devices AD812 output amplifiers in series with 47 ohms. (Approximately 80ma). The AD812s are rated short circuit proof up to package power dissipation limits.

4.5.8       The IBM SMS card documentation specifies the following worst case high and low logic level inputs:

SDTDL

-0.65

-5.81

CTDL PNP

+1.44

-0.74

CTDL NPN &

TRANSLATE

-5.26

-7.44

DTDL

+1.44

-5.50

Note: some SMS cards have more than one input signal level and these cards may not be testable with this tester. Switch positions 1 to 4 select test levels as above. Position 5 is a spare, but contains the pots to set any desired levels. Position 6 selects the front panel pots.

4.5.9       Signal rise and fall times are limited by the internal circuitry of the tester. The inherent slew rates of the video clamp amp (AD8036) and output stage (AD812) may be as fast as 20ns/12v.

4.5.9.1  (TBD) It is possible to offer other fixed or switch selectable slower slew rates if reviewers deem this advantageous for testing

4.6            SCOPE SYNC is provided on a BNC connector driven by a 74HC signal in series with 50 ohms derived from the counter binary state 1111 decode. Negative going edge on entering state 0000.

4.7            The counter CLOCK input is also provided on a scope probe connection point by a buffered 74HC signal in series with 100 ohms. This facilitates delay time measurements of SMS outputs.

4.8            A 16 position rotary switch connects SMS pins A thru R to a scope connection point for 10megohm impedance scope probe.

4.9            The test signal derived from the low order (2^0) bit of the counter is provided as a scope probe second channel output, TEST SIGNAL so the levels of the test signals can be observed on a dual trace scope if adjusted while the card is under test.

 

5.0            Breadboard interconnect area

5.1            Solderless breadboards are used to interconnect the test signals, power supplies, and loads if needed with the card under test. See Jameco part number 194299.

5.2            The breadboard area consists of a dual 63 five pin bus section used to develop a test procedure or to setup a test for modules, and 4 power busses each 63 pins in length.

5.3            The top section of 63 5 pin busses contain (one pin is used for connection to internal circuitry)

5.3.1       16 SMS module pins connect to 16 four alternate pin busses. The spacer busses are electrically floating. (busses 1 to 32)

5.3.2       5 dual power and ground buss of 4 pins each, spaced one bus (busses 35 to 48)

5.3.3       The remainder of the top section may be used for breadboard test circuits (busses 50 to 63)

5.4            The bottom section of 63 5 pin busses is dedicated to test signal connections and to load resistors. Test signals are provided on pins 1,3,5,7. The 28 available load resistors are jumpered from the appropriate power buss strips to alternate 5 pin busses, thus using 56 of the available busses. (Busses 13 to 63)

 

6.0            Loads

6.1            The following ˝ watt load resistors are provided:

Quantity

Value - ohm

Power supply voltage

6

 

430

-12

4

680

+6

4

430

Ground

6

1600

-12

6

560

-6

Note: These load values were consolidated to favor higher load currents by up to 50%, thus providing some margin testing of the output transistors gain and Vce(sat).

 

7.0            (OPTIONAL FUTURE FUNCTIONALITY- tbd) Per SMS card type, a removable “personality” crossbar connector is a VME style 96 pin connector (3 rows of 32 pins).

7.1            The crossbar connector may be custom built for each frequently tested module. The personality connector is configured by wire-wrapping the appropriate pins together. Its connections are in parallel with any jumpers on the solderless breadboard.

7.2            All of the SMS pins and breadboard available test signals, loads, and power supplies are connected to a 96 pin chassis mounted connector.

7.3            Mating 96 pin male pin plugs with wire wrap tails are wired to preserve the test setup for each module type worthy of the effort. Each plug should be marked for the module(s) it tests.

7.4            Personality connector pin arrangements TBD.

 

8.0            Documentation of the test procedure should by provided by the test developer and include

8.1            SMS logic diagram with test signals noted

8.2            Test procedure write up

8.3            Appropriate HIGH and LOW normal test signal voltages

8.4            Worst case/do not exceed HIGH and LOW levels

8.5            Scope traces of correct operation of outputs

8.6            Wiring list for the wire wrap plug if such a plug is constructed

 

9.0            Power supplies

9.1            Four built in supplies, +12, +6, -6, and –12 for the card under test and additionally +5, +15, and -15 for tester circuitry. The voltages are provided by linear regulators operating from two salvaged notebook PC “brick” bulk 19 volt switching supplies.

9.2            Each supply has a fixed voltage output +/- the 4% tolerance packaged IC regulator tolerance.

9.3            Nominal current is approximately 300ma per supply available to the card under test. Short circuit capacity of each supply exceeds 1amp.

9.4            Supplies are short and over-temperature proof per the 78/79xx design and TO-220 package capabilities of the series regulators. A small fan provides cooling to the internal supplies and circuitry. Each regulator has a clip on heat sink.

 

10.0         Mechanical packaging

10.1         All 74HC logic and power supplies are internal to the box.

10.2         120 v 60 Hz power with an ON-OFF switch

10.3         4 pole SMS card power ON/OFF, turns on/off +/-12 and +/-6 volts

10.4         The scope pin select switch is connected to signals via a connector so it can be easily replaced.

10.5         The SMS card connector is connected to signals via a cable and connector so it can be replaced.

10.6         The personality tester connector is wire wrapped at level 3 so it can be replaced.

 

 

Controls & connectors

 

Power provided on the breadboard area

+12, +6, GND, -6, -12

 

Card pins provided on the breadboard area

Pins A-R of the SMS cards

 

Controls

Main Power ON-OFF (2 pos dpst switch)

OSC FREQ (pot)

OSC INT – OSC EXT (2 pos spdt switch)

SMS power (2 pos 4pst switch)

ALL HI – OSC – ALL LO (3 pos spdt switch)

COUNTER – PULSE (2 pos spdt switch)

 

Indicators

LED (red) Test level error (maybe a beeper also) i.e. PULSE HI < PULSE LO

LED (green) main power on

LED (red) SMS card under test power applied

 

Connectors

Power cord 120v 60Hz

Scope sync BNC

Personality – 96 pin VME (not in V1)

SMS card – 16 pin SMS edge connector

SCOPE OUTPUT 1 – probe clip on post with output from 16 position rotary switch, card pins A –R

SCOPE OUTPUT 2 – probe clip on post with test signal from bit 2^0 of counter

 

Breadboard area

13 columns of 5 pins Buss

 

GSaviers CTDL PNP cards tested_files
CTDL PNP
Type 1401 qty spares description # elements ins per outs per
3JMX 51 46 TWO WAY GATE W/O LOADS 4 2 WIRE OR
4JMX 54 53 TWO WAY GATE W LOADS 4 2 WIRE OR
CG 27 1 TWO WAY AND NO LOADS 3 2 1 NL
CGVV 38 8 TWO WAY AND ONE LOAD 3 2 1 (2 NL)
CGWW 49 25 TWO WAY AND 3 2 1
CGVW 29 14 TWO WAY AND TWO LOADS 3 2 1 (1 NL)
CJVU 2 0 3 WAY AND ONE LOAD 2 3 1 (1 NL)
CJWF 111 79 3 WAY AND NO LOADS 2 3 1 (2 NL)
CJWV 18 3 3 WAY AND 2 3 1
CJYC 47 32 3 WAY AND 2 3 2
CQ 31 23 ONE WAY NO LOADS 4 1 1 (4 NL)
CQYG 18 3 ONE WAY PNP 4 1 1 (3 NL)
CQZT 51 55 ONE WAY 2 LOADS 4 1 1 (2 NL)
CQZV 59 43 ONE WAY PNP 4 1 1
JF 3 0 HIGH SP ONE WAY NO LOADS 4 1 1 (4 NL)
JFVA 2 1 ONE WAY ONE LOAD 4 1 1 (3 NL)
JFVN 12 1 HIGH SP ONE WAY 2 LOADS 4 1 1 (2 NL)
JFVP 11 1 HIGH SP ONE WAY ALL LOADS 4 1 1
JG 8 1 TWO WAY AND NO LOADS 3 2 1 (3 NL)
JGVV 7 1 HIGH SP TWO WAY AND 1 LOAD 3 2 1 (2 NL)
JGVW 2 2 HIGH SP TWO WAY AND 2 LOADS 3 2 1 (1 NL)
JGWW 20 2 HIGH SP TWO WAY ALL LOADS 3 2 1
JH 12 1 HIGH SP 3 WAY AND NO LOADS 2 3 1 (2 NL)
JHVU 12 2 HIGH SP 3 WAY ONE LOAD 2 3 1 (1 NL)
JHWV 7 1 HIGH SP 3 WAY AND ALL LOADS 2 3 1
KA 29 21 ALLOY INDICATOR DRIVER 4 1 1 (4 NL)
TDB 3 0 SDTRL DIST LINE TERMINATOR 4 1 1
713

GSaviers CTDL NPN cards tested_files
CTDL NPN
Type 1401 qty spares description # elements ins per outs per
2JMX 49 34 TWO WAY GATE W LOAD 2 4 1 WIRE OR
CEH 22 8 INVERTER LATCH 2 3 2
CH 59 13 TWO WAN AND NPN NO LOADS 3 2 1 (3 NL)
CHVU 2 0 3 WAN AND NPN 1 LOAD 2 3 1 (1 NL)
CHVV 37 7 TWO WAY AND NPN 1 LOAD 3 2 1 (2 NL)
CHVW 36 14 TWO WAN AND NPN 2 LOADS 3 2 1 (1 NL)
CKVU 44 17 3 WAY AND NPN 1 LOAD 3 2 1 (1NL)
CKWF 76 34 3 WAY AND NPN NO LOADS 2 3 1 (2 NL)
CKWV 17 2 3 WAY AND NPN 2 3 1
CHWW 56 0 TWO WAY AND NPN 3 2 1
CKYC 44 9 3 WAY AND NPN 2 3 1
CR 23 12 ON WAY NPN NO LOADS 4 1 1 (4 NL)
CRYG 10 4 ONE WAY NPN ONE LOAD 4 1 1 (3 NL)
CRZT 50 41 ONE WAY NPN TWO LOADS 4 1 1 (2 NL)
CRZV 51 24 ONE WAY NPN 4 LOADS 4 1 1
JJ 1 1 HIGH SP ONE WAY NO LOADS 4 1 1 (4 NL)
JJVA 8 2 HIGH SP ONE WAY 1 LOAD 4 1 1 (3 NL)
JJVN 7 3 HIGH SP ONE WAY 2 LOADS 4 2 1 (2 NL)
JJVP 10 2 HIGH SP ONE WAY ALL LOADS 4 1 1
NU 6 2 POWER INVERTER P TYPE 2 2 1
608

GSaviers STDTL cards tested_files
STDTL
Type 1401 qty spares description # elements ins per outs per
DEF 5 1 FOUR 2 WAY N 4 2 1
DEG 2 0 FOUR 2 WAY N 4 2 1 NL
DEJ 1 0 THREE 3 WAY N 3 3 1 NL
DFR 14 1 NON-INV PWR DRV 4 1 1
DGT 20 1 2 WAY LOGIC 4 2 1
DGS 14 0 IND DRV 6 1 1
DGU 13 0 2 WAY LOGIC 4 2 1 NL
DGV 16 2 3 WAY LOGIC 3 3 1
DGW 10 1 3 WAY LOGIC 3 3 1 NL
DGX 20 1 5 WAY 2 5 1
DGY 7 1 5 WAY LOGIC 2 5 1 NL
DGZ 19 0 10 WAY 1 10 1
DHA 7 0 10 WAY LOGIC 1 10 1 NL
DHB 8 1 INVERTER LOW SP 6 1 1
DHC 9 0 INVERTER LOW SP 6 1 1 NL
DHH 4 0 DBL LVL BLOCK 2 4 1 NL
DHF 15 0 TRIGGER 2 4 2
DHG 7 0 R & W REGISTER 1 7 5
DHJ 4 0 MUP NUMBER 4 1 8 1
DHK 7 0 LATCH W GATE OUT 1 7 5
20 types 202

Updated Nov 24, 2013