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Logic Circuit Discussions


Contents:
- Inductor in circuit ??
- Logic families


also see SMS Logic Levels

Inductor in circuit ??
re: IBM-1401-Theory-of-Operation (by Guy Fedorkow)
Marc Verdiell wrote: - On Aug 3, 2015, at 10:09 PM,
Guy, {Fedorkow}
{...}
By the way, I had a question no one could answer for sure. On the SMS circuits, there most often is a 56 uH inductor in series with the resistor load in the collector. What is that for? Some wild guesses we came up with:
- To speed up transition time and counteract the large capacitance of early transistors?
- To act as a choke to protect the power supply rail from switching parasitics?

Anyone knows?

Marc Verdiell

Robert Garner responded:
Marc,

> I had a question no one could answer for sure. On the SMS circuits, there most often is a 56 uH inductor in series with the resistor load in the collector. What is that for?

I've assumed that the series inductor in the collector pull-up is used to (slightly) speed up the (initial) transition times. As the transistor turns off and current through the inductor decreases, that should slightly increase/boost the output voltage, and vice versa when the transistor turns on.

I've wanted to spice the circuit to see just how much of a difference a 56 uH inductor actually makes. (And I wonder how high it can go before the circuit rings/oscillates with transistor, output, and stray capacitances...) And we could just measure the effect by shorting the inductor (or putting in larger ones). I suspect it doesn't make a big difference (I'm a little surprised it was actually done.)

- Robert

p.s. I've cc'd Ron Crane, who knows the answer to all analog questions.. ;-)
And Jud, who may have done timing on the circuits back then.

Ed Thelen commented
We used to call inductors placed there "speed-up" inductors, they helped sharpen the edges of pulses.

The capacitor C8 in the base circuit could be called a "speed-up" capacitor,
- somewhat bypassing the turn-on delay of the diode
- or if there was a bias or protective resistor in the position of the diode

I have a cute little kit called "Analog Discovery" from "Digilent" with many types of components which I should fire up, but the inductors are limited to 1uH and 1mH and I'm too lazy to scale it, and really cannot guess a typical parasitic capacitance in the output circuit. (They have lots of other fun things, including op-amps, transistors, a microphone, an accelerometer, ... )
The multipurpose USB "head" includes USB scope, voltages sources, signal sources, ... is really neat !!

From: Ken Shirriff < ken.shirriff@gmail.com > - Aug 04, 2015 7:59 am
For the inductor, the SMS document Transistor Component Circuits p45 {marked page 47} says: The peaking coil compensates for output capacitance, so that optimum square-wave response is realized.

I picked up an IBM 709 tube module, which uses an interesting component that looks like a fat resistor, but it's a 8.2K resistor and a 750uH coil in parallel in one package.This is a peaking circuit that keeps the plate current flowing long enough.

Ken


Logic families - an e-mail sequence - I may be mixed up who said what to whom when :-((
But we are not in Judge Judy's court ;-))
Here's a 2009 note from Bob Feretich on TAU levels.
I am not the right guy to write about the TAU interface circuits. I have a good understanding of how the TAU works on a cycle by cycle basis (system level understanding), but its special circuits are a mystery.

All I can say is that the interface is driven by emitter follower drivers and that current flow rather than voltage levels is used to represent high and low values. (The difference between high and low levels is only a few hundred millivolts.)

I seem to remember that emitter follower drivers have very low output impedance.

The internal circuits in the TAU are different from the CPU. The CPU logic uses alternating ranks of U (0 to -12V) and T (+6 to -6v) level logic. The logic thresholds were set in the middle of these voltage ranges, so there were several volts of noise margin. All TAU logic switches between 0 to -6v. On one side (the side varies with NPN and PNP circuits) the noise margin is only 0.5v. I believe that is why we have found more circuits failing from leaky transistors in the TAU than in the CPU. The transistors in the CPU are probably just as leaky, but the large noise margins in the CPU permit them to continue to perform logic functions correctly.

Regards,
Bob

On Sat, Aug 1, 2015 at 6:08 PM, Robert Garner wrote:
N logic levels are higher than P logic levels. With the 1401's CTDL logic, the N level is given the symbol T, and switches relative to a reference voltage of 0 volts. The P level is given the symbol U and switches relative to a reference voltage of -6 volts.
      
     Perhaps better to explicitly state the high and low voltage levels?
      And are you sure you want give them new names, i.e., "N and P logic levels"?
       
      Perhaps we should just stick with the original names, "T and U logic levels"?
      (There are other family signaling levels that use alternating NPN and PNP transistors..)

Yes, that sounds a lot simpler.

I looked at the 729's SMS cards and it seems to use a mixture of current-mode (P and N), CTRL (R and S), and SDTRL (voltage-mode, Y) signals.

Ken

     How about this:
      "T signals switch between -6V to +6V (threshold is 0V) and
      U signals switch between  -12V to 0V (threshold is -6V).
      The switching circuits provide about 4.6V of noise margin.
       
      Note that the TAU voltage levels are different, as they are current switching circuits.
     (A switching technology invented at IBM.)
      The TAU was hoisted from the 7070 mainframe, and also likely used in the 7090).
      I can't recall their names (sitting outside here on a nice bay area day.  ;-),
          but Carl or Bob, cc'd, will.   ;-) 
 

On Aug 1, 2015, at 5:33 PM, Ken Shirriff wrote:
One other thing, for Figure 12, the ALD logic block, the second thing below the block (e.g. 2B) is the column/row on the ALD page. I've never seen that mentioned, but I eventually figured it out.

On page 25, there's a discussion of N and P gates. Here's my understanding. It may be confused, so I'll throw it out to the "mob" for comments:

A card output can be non-inverted (called in-phase or "in ") or inverted (called out-of-phase or "out "). For example, for an AND gate, the in-phase output would provide AND, while the out-of-phase output would provide NAND.

On the ALD, out-of-phase outputs leave the upper half of the block, while in-phase outputs leave the lower half out the block. In-phase outputs can be prefixed with +, while out-of-phase outputs can be prefixed with -.

Circuitry typically alternates NPN gates and PNP gates to simplify the hardware. These gates produce two different voltages, so there are two types of signals. The output from an NPN transistor is called an N level output, and the output from a PNP transistor is called a P level output.

N logic levels are higher than P logic levels. With the 1401's CTDL logic, the N level is given the symbol T, and switches relative to a reference voltage of 0 volts. The P level is given the symbol U and switches relative to a reference voltage of -6 volts.

On 8/2/2015 7:27 PM, Robert Garner wrote:
Carl,

Might be good to write a translation and explanation of the odd concept behind the SMS generation logic, that of using complementary (NPN then PNP) sequences of gates and having dual sets of voltage thresholds as a result. By the time IBM rolled out the successor generation, SLT, they did away with all that and had a modern looking single definition for logic levels...

The only explanation I can come up with as to why CTDL input and output levels are offset by 6V (half their range) was in order to implement a very robust logic-level noise margin/tolerance. At the time, a perceived useful design paradigm was that logic designers would alternately cascade "Plus AND, Minus OR" (AND logic) with "Minus And, Plus OR" (NAND logic) for inversion. The easiest way to implement that is with complementary NPN and PNP transistors, but that doesn't ordain offset logic levels. For instance, I see that the early SLT family uses complementary transistors, but not offset levels.

Per the "Transistor Component Circuits" manual (CTDL starts on pg 105) ...
http://ibm-1401.info/Form223-6889-TransistorComponentCircuits.pdf

... a valid low U level is anything from -7.4V to -12V, and a valid high T level is anything from 1.4V to 6V, both representing a remarkable 4.6V noise margin.

One could view this as a 9.2V combined noise margin out of 12V signal swing (77%).

I'm not familiar with as much noise margin offered by any other logic family!
With this 6V offset, the CTDL circuits are more immune to weak transistors or capacitively or inductively induced noise
(important consideration given the long single-ended wires used to interconnect the gates).
Perhaps this is a key reason the 1401 was so reliable (in spite of using less-than-consistent Germanium transistors).

From the CTDL introduction on page 6: "In order to make sure that the diodes are reverse biased when the transistor is on, the input and output voltage references differ by 6 volts." It would have been more clear it the author had written: "In order to make sure that the diodes are reversed biased even with degraded logic levels, the input and output voltages differ by 6 volts, thus guaranteeing transistor saturation even under noisy conditions."

A key drawback of the offset levels is when you need to invert a level just because you don't have its complement. I've asked Ron Williams, based on his experience of viewing so many 1401 ALDs: What percentage of the gates are nothing but converters between U and T levels? He estimated about 15%. (Someone care to inventory them all? ;-)) Btw, how many logic gates comprise a 1401? With ~2400 SMS cards in the CPU and (supposedly) 10,600 transistors, guessing, perhaps about 6000 gates?

Looking at the SLT logic (for the first time ;-), given a single 0 - 3V swing, its diode-transistor logic offers a lower noise margin, perhaps just a transistor's base-emitter voltage drop, say 0.6V min, for a combined margin of 1.2V out of 3V (40%). It would be even less with the higher voltage logic levels. So the 1401's CTDL circuits could have a 77/40 or nearly 2x better noise margin compared to the 360's SLT circuits (which also had much shorter signal lines).

Jud ===> Given that your first job at IBM was to characterize transistor behavior, ;-)
do you recall the reasons for adopting the CTDL family with its offset logic levels (first by the 7070)?
Over the years, I haven't been able to find any documents, patents, anything, that explains or rationalizes why IBM chose CTDL with offset levels.

Cheers,

- Robert

p.s. Someone might feel compelled to update Wikipedia's entry on diode transistor logic (which, oddly, has several references to the 1401 !) ;-))
https://en.wikipedia.org/wiki/Diode%E2%80%93transistor_logic

p.p.s. Some more informative diagrams from the transistor circuits manual...

On Aug 2, 2015, at 11:10 AM, Claunch,Carl wrote:
Might be good to write a translation and explanation of the odd concept behind the SMS generation logic, that of using complementary (NPN then PNP) sequences of gates and having dual sets of voltage thresholds as a result. By the time IBM rolled out the successor generation, SLT, they did away with all that and had a modern looking single definition for logic levels, thus one NAND gate could connect to the next without requiring dual versions of NAND gates at U and T levels. The basic SLT gate is very similar to the SMS gate diodes for each signal input line whose other side is tied together and connected (through intermediate parts) to the base of an inverter transistor. Unlike in SMS, two of the same SLT gate circuits could be chained together, much like the families most people are familiar with such as TTL, and the CMOS flavors.

Carl


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