Sheet 1PIC and Analog InterfacesBob Feretich1.11401 Team1 of 816/16/2006-1364000000Arial-1004000000Arial-1364000000Arial-1364000000Arial-1364000000Arial-2194000000Arial-944000000Arial-1254000000Arial-944000000Arial-1364000000Arial-1364000000Arial00000010000005-1000000DLP245PLH2U?Signal Header 21$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0F6F4F2H6H4F0A4A2A0GNDaGNDcH0H2DB0DB2DB4DB6F7F5F3H7H5F1A5A3A1GNDbGNDdH1H3DB1DB3DB5DB7DLP245PLH3U?Signal Header 31$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0UVCCSVCCaSVCCbG0G3B0B1B3GNDaJ0J1J2J3J4LEDJ6J7E0E1E2E3E4E5E6E7GNDbC0C1C2C3C4C5C6C7DLP245PLH4H?Programming Header1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0SVCCGNDB6B7MCLRConn60U?60 Pin Flat Cable Connector1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0A1A3A5A7A9A11A13A15A17A19A21A23A25A27A29A31A33A35A37A39A41A43A45A47A49A51A53A55A57A59A2A4A6A8A10A12A14A16A18A20A22A24A26A28A30A32A34A36A38A40A42A44A46A48A50A52A54A56A58A60138U?3 to 8 decoder1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC`G2BY5Y3Y2Y1Y0`G2AG1CBAY4Y6Y7244U?3-state line buffers2$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0Yb2Yb1Yb0Ya2Ya1Ya0Ib3Ib2Ib1Ib0Ia2Ia1Ia3Ia0`O`EaGNDVCCYa3Yb3`O`Eb688U?8-bit Identity Comparator1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCCOA5A4A3A2A1A0A6A7B5B4B3B2B1B0B6B7G373U?Octal D-Type Latches1`O`EGNDVCCQ5Q6Q3Q2Q1Q0D5D4D7D6D3D2D1D0Q7Q4E11FF00000000FF0000000000002080000000004040C0208020FFFFFFSelectLatched_SelectData_BusGNDGNDGNDGNDGNDGNDTRK_SHIELDSGNDTWRITEDATAVCCGNDGNDSheet 2Response signalsBob Feretich1.01401 Team211/3/2006-1004000000Arial-1364000000Arial-24114000000Arial-944000000Arial000000100000010000001-100000075188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND00U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND00U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND00U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND00U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND00U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCLVCCH1A1Y2Y2A2B3Y3A3B4Y4A4BGND04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A75188U?RS232 Driver4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0-12V+12V1A1Y2Y2A2B3Y3A3B4Y4A4BGNDRESARY2KU?2K Resistor Array4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1C2A2C3A1C4A4CRESARY1KU?1K Resistor Array4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1C2A2C3A1C4A4CDA_CAU?Cathode Input4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1C2A2C3A1C4A4CDA_ACU?Anode Input4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1C2A2C3A1C4A4C11FF00000000FF0000000000002080000000004040C0208020FFFFFF+P Drivers-N DriversAll inputs are sourced from Sheet 1Sheet 3+P Input Level ConversionBob Feretich1.01401 Team311/3/2006-1004000000Arial-1364000000Arial-1364000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial0000001-100000026LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2Bz26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2Bz04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6APTERMT?+P Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2S-6SLD-12V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16SPTERMT?+P Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2S-6SLD-12V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16S26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGNDPTERMT?+P Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2S-6SLD-12V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16S26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGNDPTERMT?+P Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,02D2S-6SLD-12V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16S1D1S11FF00000000FF0000000000002080000000004040C0208020FFFFFF-6V-6V-6V-6V-6V-6VGNDGNDSelect-6V-6V-6V-6V-6V-12V-6VGNDGNDSheet 4-N Input Level ConversionBob Feretich1.01401 Team411/3/2006-1004000000Arial-1364000000Arial-1364000000Arial-1364000000Arial-1364000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial0000001-100000026LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2Bz26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2Bz04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGND26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGNDNTERMT?-N Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2SGND+5V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16S26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGNDNTERMT?-N Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2SGND+5V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S13D13S14D14S15D15S16D16SNTERMT?-N Terminator17$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D1S2D2SGND+5V3D3S4D4S5D5S6D6S7D7S8D8S9D9S10D10S11D11S12D12S14D14S15D15S16D16S13D13S11FF00000000FF0000000000002080000000004040C0208020FFFFFFGNDTWRITEDATAGNDGNDGNDGNDGNDGNDGNDGNDGNDVCCGNDGNDGNDGNDGNDGNDGNDGNDSheet 5Monitored Signal Level ConversionBob Feretich1.01401 Team513/8/2006-1004000000Arial-1364000000Arial-1364000000Arial-944000000Arial-2194000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-944000000Arial-1254000000Arial-1154000000Arial-944000000Arial-1664000000Times New Roman000000100000010000001000000100000010000001-100000004U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGND06U?Hex Inverters6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A26LS32U?Quad EIA-442/3 Rcvr w/tri-state4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01A1Y2Y2A3Y3A4Y4A1B+-E1`E23B4B2BzVCCGNDTHRESHOLD_ADJUSTR?Threshold Adjustment1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0TP16935010010uf20v+RPACK10R?10-pin Resistor Pack1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,011FF00000000FF0000000000002080000000004040C0208020FFFFFFMonitored +P SignalsMonitored -N SignalsGNDGNDGNDGNDGNDGND-12V-12VR-Pack compensates for26LS32 current drain.Sheet 6Tape Channel ConnectorsBob Feretich1.01401 Team612/20/2006-1004000000Arial-1364000000Arial-1254000000Arial-1254000000Arial-1254000000Arial-1254000000Arial-1254000000Arial-844000000Arial-944000000Arial-944000000Arial-1254000000Arial0000001000000500000020000002-1000000Conn60C?60 Pin Flat Cable Connector1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0A1A3A5A7A9A11A13A15A17A19A21A23A25A27A29A31A33A35A37A39A41A43A45A47A49A51A53A55A57A59A2A4A6A8A10A12A14A16A18A20A22A24A26A28A30A32A34A36A38A40A42A44A46A48A50A52A54A56A58A60CAP_BRDTCRESPONCE LINE CAPACITORS12$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D2D3D4D5D6D7D8D9D10D11D12D5 uFGNDCAP_BRDTCRESPONCE LINE CAPACITORS12$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,01D5 uF7D2DGND3D4D5D6D8D9D10D11D12D11FF00000000FF0000000000002080000000004040C0208020FFFFFFGNDTRK_SHIELDSGNDGND-6VGNDGND-6VSheet 7LED Board ConnectorBob Feretich1.01401 Team712/14/2006-1004000000Arial-1364000000Arial-1364000000Arial-1984000000Arial-1364000000Arial-944000000Arial-944000000Arial-1254000000Arial-1364000000Arial0000001-100000004U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6ALEDCON34C?34-Pin LED Connector1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0TriggeredGoBackwardsHi_DensS_LoDensS_HiDensRewindingRewindWritePlsRwd&UldWriteLRCTapeIndWriteAtLoadPtSetWriteMod5+6ReadSel&Rdy4SetReadSel&Rdy2NCSELECT1 2 3 4 5 6C B A 8 4 2 1Write DataDiagnostic/PolarityC B A 8 4 2 104U?Hex Intervers6$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A04U?Hex Intervers6$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6A11FF00000000FF0000000000002080000000004040C0208020FFFFFFCABLE TO LED BOARDLEDs should be connected to VCC through a 150 Ohm resistorTWRITE_DATASheet 8Test Connecter & Power DistributionBob Feretich1.01401 Team812/25/2006-1004000000Arial-1364000000Arial-1364000000Arial-1364000000Arial-1364000000Arial-944000000Arial-1254000000Arial-1254000000Arial-1984000000Arial-1984000000Arial-1984000000Arial-1984000000Arial-1984000000Arial-1254000000Arial000000100000010000005-1000000DLP245PLH1H?Power Header1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0XVCCaGNDaXVCCbGNDbGNDcGNDdX35aGNDeX35bGNDfRE1R?Small Resistor1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,000U?Quand NAND gates4$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCCGND1A1B1Y2Y2A2B3Y3A3B4Y4A4B04U?Hex Intervers6GNDVCC1A1Y2Y2A3Y3A4Y4A5Y5A6Y6AHDR60C?60 Pin header1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0A1A3A5A7A9A11A13A15A17A19A21A23A25A27A29A31A33A35A37A39A41A43A45A47A49A51A53A55A57A59A2A4A6A8A10A12A14A16A18A20A22A24A26A28A30A32A34A36A38A40A42A44A46A48A50A52A54A56A58A60PwrConn12C?12-pin Power Connector1$$SPICE_PROLOG_PRIORITY50000020,0$$SPICE_EPILOG_PRIORITY50000020,0Packagepackage name for PCB layout0000010,0VCC1VCC2GND1GND2GND3GND4+12V1+12V2-12V1-12V2-6V1-6V211FF00000000FF0000000000002080000000004040C0208020FFFFFFVCCGNDVCCVCCVCCVCCSPARESPULL UPSPOWER TO PICGNDTEST POINT CONNECTORGNDBoard Power ConnectionVCCGND+12V-12V-6VCable Color CodeREDBLACKYELLOWBLUEWHITE